BACKWARD COMPATIBILITY & EMOTION ENGINE: http://en.wikipedia.org/wiki/Emotion_Engine
The Emotion Engine is the name of the CPU used in the Sony PlayStation 2. It was jointly designed by Toshiba and Sony, and began mass production in 1999. According to MicroDesign Resources, it is two times the speed of a 733 MHz Pentium III, and 15 times the speed of a 400 MHz Celeron at handling tasks like full-motion video (SIMD).

The Emotion Engine (EE) is off when PS3 games use the PS3 hardware.  It is was hoped that in the future, developers will use some of the processing power of the EE to free up the Cell CPU for more important tasks with PS3 games.  However, this all changed when the European version of the PS3 systems were assembled without the EE hardware.  So, it would be foolish now, for developers to program code for a chip that will not exist anymore.  Sony had planned on removing the hardware well before the European launch of the PS3.  Newer versions across the globe will not have the EE hardware. Oh, and before you ask "What good would the EE do to help the PS3?"  With the EE hardware, there should be enough bandwidth to access the RSX for copying the raw frame buffer.

Now, the big argument is: Sony promised gamers this backwards compatibility. It's yet another broken promise.   Sony only did this to save about $30 per system.  Well, if the backward compatibility worked 100% from the start, it would not be such a big deal.  There is no real sense in keeping hardware that did not work 100%, when software emulattion would be just as unreliable as it was to begin with, and cheaper.  It was a huge selling point, that the PS3 played the entire library of PS2 games out of the box. This was one of the few advantages it had over the Xbox 360.

The reality of it is, if you want to play PS2 games, you probably already have a PS2. Even with the emotion engine in the US and Japan PS3s, there were many complaints that PS2 games didn't look very good on the PS3 anyway. You are simply better off playing them on the PS2.

QUOTES FROM SONY FOR THE EUROPEAN COMSUMER :
“The original PS3 used the Emotion Engine/Graphics Synthesiser to emulate PS2 titles,” commented an unspecified Sony representative in an interview posted on the company's Three Speech 'semi official' blog. “With the latest European specification we have removed the Emotion Engine, retaining the graphics chip. This has an impact on the number of PS2 titles that will be backwards compatible.”

While no specific reason for the shift from hardware to software emulation of PS2 titles was cited by Sony in the interview, many have speculated the move was made in an effort to cut costs. This theory was given further credence by Sony Computer Entertainment Australia managing director Michael Ephraim, who commented to consumer website GameSpot that the move presented a cheaper, though admittedly less effective alternative for the technology giant.

"Clearly cost is one of the [reasons]. If software is cheaper than the cost of the chip, then why not do that?" commented Ephraim. "We will be working on delivering backward compatibility through software emulation. The software-emulation list will grow, and there's a Web site people can check to see what games are backward compatible. It will be a progressive emulation."

Approximately 98 percent of PlayStation and PlayStation 2 titles are backwards compatible with the U.S. and Japanese consoles, though Sony has not yet made available a list of which games will work on the PAL PlayStation 3. The company did note that such a list will be released care of an official website, though this site is not expected to go live until the console's March 23 debut.

While the lack of a definitive list is sure to upset some who weigh the issue of backwards compatibility heavily in their decision to purchase the console, Sony does note that it is “assessing the extent of backward compatibility, and will continue to do so right up until launch.”

Last edited by Powerslave (2007-04-05 16:57:43)

Xecuter PS3 HDXT

The Xecuter PS3 HDXT is a caddy type frame that plugs into the PS3 internally where the 2.5" Sata drive would normally slot. You then clip on the matching faceplate and bingo you now have a clean external Sata connection. No frills and no fuss. You can now add any hard drive you wish and connect it any way you wish.

You will have to power your new HDD externally, either with a 220/110V to molex/sata-power adapter or you can buy one of those external/cased SATA HDDs from companies like LaCie, Seagate and others.

Also note that once your PS3 is connected with an external drive you can no longer put your console vertically as the adapter is on the bottom.

The 'PS3 HDXT' comes with the caddy adapter and a front plate with hole for the external SATA connector.

The 'IDE to SATA Adapter' (sold separately) allows you to easily connect any IDE HDD with your PS3. The 'IDE to SATA Adapter' comes with the converter PCB to translate IDE into SATA and a cable to power this PCB from a molex power. 

A 3.5 500Gb Exernal IDE drive was successfully tested.

Last edited by Powerslave (2007-04-23 15:59:59)

DETAILED LOOK AT THE PS3 - Updated 09/23/08

Model Options
   
   * 20GiB (USA/JAP ONLY = No PAL Release) (Discontinued April 11, 2007)
      > No Card Reader
      > No WiFi
      > No Chrome Trim
      > Hardware Backwards Compatibility
         > EE+GS
   * 40GiB (PAL/NTSC) Oct. 10, 2007 - Japan Nov. 11, 2007  - Oct. 10, 2007 Other Regions
      > 65nm CPU
      > White Case (Asia Only)
      > No Card Reader
      > PS1 Backward Compatibility
      > No SACD
      > Chrome Trim
      > WiFi
      > Only 2 Front USB Ports
   * 60GiB (NTSC) (Discontinued August 6th, 2007 on Price Drop notice - Production was halted)
      > Hardware Backwards Compatibility
         > EE+GS
      > (PAL) Software Backwards Compatibility
         >GS
      > All Options
   * 80GiB - July 9, 2007 (USA ONLY)
      > All Options
         > Software Backward Compatibility - No PS2 Hardware
   * 80GiB - September 2008
      > No Backward Compatibility
 
   * 120GiB (Kiosk/Demo Units)
      > Options as specific as retail units of same MFR date & region.
         > Unlock Code required to Access most features.
         > Built to freeze up on purpose - so that people won't play it all day long.
            > Specifically during Motorstorm.
         > Not for resale.
         > Can get on-line firmware updates, but unlock code changes

   * ???GiB Debug (TEST) Unit
      > No Blu-Ray movie playback
      > Runs unfinished code from burned BR-Ds
     

Region Information

   * PS3 Titles = Region Free (reportedly, at developer's disgression)
   * PS2 Titles = Region Locked
   * PS1 Titles = Region Locked
   * DVD Movies = Region Locked
   * BR-D Movies
      > A/1 North America, Central America, South America, Japan, North Korea, South Korea, Taiwan, Hong Kong and Southeast Asia.
      > B/2 Europe, Greenland, French territories, Middle East, Africa, Australia and New Zealand.
      > C/3 India, Nepal, Mainland China, Russia, Central and South Asia.


The following internal specifications are very detailed!  Most specs taken from FCC documents, Sony, and IBM.

CPU: Cell Broadband Engine - 90nm Process before March 2007 (65nm > March '07)

    * PowerPC-base Core @3.2GHz (Prototype ran at 4.66Ghz)
      > 64 bit, "Power Architecture" processor
      > Dual issue, dual threaded, in-order processor.
      > 235 square mm
      > 235 million transistors
      > Rambus XDR and FlexIO technology allow up to 100 gigabyte/s memory transfer rates.
      > 90nm Process CMOS SOI
         > 65nm CMOS SOI Process Started March 07
            - 6GHz at 1.3V
            - Dual power supply; enhances SRAM stability and performance using an elevated  array-specific power supply, while reducing the logic power consumption.
      > Power consumption has been estimated at 60 - 80 Watts at 4 GHz
    * 9 Core CPU
       > 1 Power Processor Element (PPE) - Acts as Controller (PowerPC Core)
          > The PPE is dual threaded
             > RISC architecture
             > Fixed-width 32-bit instruction format
             > 64-bit general purpose register set (GPR)
             > 64-bit floating point register set (FPR)
             > 128-bit Altivec register set
           > Additional instructions relating to control of the SPEs
       > 8 Synergistic Processor Elements (SPEs) with 256KB "Local Stores" per Core
          > Can support up to 4 GiB of local store memory
          > Each SPE capable of 32 GigaFlops (32 bit)
          > RISC architecture
          > Fixed-width 32-bit instruction format
          > 128-bit, 128 entry register only
             > Scalar data types, from 8-bits to 128-bits
                > Or SIMD computations on a variety of integer and floating point formats
    * 1 VMX vector unit per core
    * 512KB L2 cache
    * 7 x SPE @3.2GHz
      > 1 of 8 SPEs reserved for redundancy
      > 6 SPE used for game applications
    * 7 x 128b 128 SIMD GPRs
    * 7 x 256KB SRAM for SPE
    * Element Interconnect Bus (EIB)
       > Circular ring comprised of 4 16B-wide unidirectional channels which counter-rotate in pairs
          > Each channel can convey up to three transactions concurrently
          > Each channel 16B read port and one 16B write port
          > Max 12 concurrent transactions * 16 bytes wide / 2 system clocks per transfer
       > Runs at half the system clock rate
          > Effective channel rate is 16 bytes every two system clocks
    * Direct Memory Access Controller (DMAC).
    * 2 Rambus XDR memory controllers
    * Rambus FlexIO (Input / Output) interface
      > Interface is organized into 12 lanes
         > Five 8-bit wide point-to-point paths are inbound lanes to Cell
         > Seven 8-bit Outbound from Cell
      > Each lane unidirectional 8-bit wide point-to-point path
      > Peak bandwidth of 62.4 GB/s (36.4 GB/s outbound, 26 GB/s inbound) at 2.6 GHz
      > Can be clocked independently
    * Test and Debug Logic
    * Total floating point performance: 218 GFLOPS
    * Capable of running at speeds beyond 4 GHz

   * Synergistic Processor Elements (SPEs)
An SPE is a self contained vector processor which acts as an independent processor.  They each contain 128 x 128 bit registers, there are also 4 (single precision) floating point units capable of 32 GigaFLOPS* and 4 Integer units capable of 32 GOPS (Billions of integer Operations per Second) at 4GHz.  The SPEs also include a small 256 Kilobyte local store instead of a cache.  According to IBM a single SPE (which is just 15 square millimetres and consumes less than 5 Watts at 4GHz) can perform as well as a top end (single core) desktop CPU given the right task.

*This is counting Multiply-Adds which count as 2 instructions, hence 4GHz x 4 x 2 = 32 GFLOPS. 32 X 8 SPEs = 256 GFLOPS

*The local store does not operate like a conventional CPU cache since it is neither transparent to software nor does it contain hardware structures that predict which data to load.

Like the PPE the SPEs are in-order processors and have no Out-Of-Order (OOO) capabilities.  This means that as with the PPE the compiler is very important.  The SPEs do however have 128 registers and this gives plenty of room for the compiler to unroll loops and use other techniques which largely negate the need for OOO hardware.

The PPE: Capable of running a conventional operating system, has complete control over the SPEs.  It can can start, stop, interrupt, and schedule processes running on any of the the SPEs. To this end the PPE has additional instructions relating to control of the SPEs. Unlike the SPEs, the PPE can read and write to main memory, and the local memories (local stores) of each SPE through the standard load/store instructions. Despite having Turing complete architectures, the SPEs are not fully autonomous and require the PPE to prime them before they can do any useful work.

Though most of the "horsepower" of the system comes from the synergistic processing elements, the use of DMA as a method of data transfer and the limited local memory footprint of each SPE pose a major challenge to software developers who wish to make the most of this horsepower, demanding careful hand-tuning of programs to extract maximal performance from this CPU.


CPU: Emotion Engine (20 & 60GiB USA/JAP Only)
   
    * Clock Frequency: 300 MHz
    * Instruction Set: MIPS III, MIPS IV Subset, 107 Vector Instructions
    * MIPS Based Core: 2 Issue, 2 64 Bit Fixed Point Units, 1 Floating Point Unit, 6 Stage Pipeline
    * Instruction Cache: 16 KiB, 2 Way Set Associative
    * Data Cache: 8 KiB, 2 Way Set Associative
    * Scratch pad RAM: 16 KiB
    * Translation Look Aside Buffer: 48 Entry Combined Instruction/Data
    * Vector Processing Unit: 4 FMAC Units, 1 FDIV Unit
    * Vector Processing Unit Registers Register: 128 Bit Wide, 32 Entries
    * Image Processing Unit: MPEG2 Macroblock Layer Decoder
    * Direct Memory Access: 10 Channels
    * Internal Data Bus: 128 Bit, 150 MHz, 2 GiB/s Maximum Effective Bandwidth
    * Memory Bus: Two 16 Bit, 400 MHz DRDRAM Channels, 3.2 GiB/s Maximum Theoretical Bandwidth
    * Manufacturing Process: 0.25 �m (0.18 �m Effective LG, 4 Layer Metal, CMOS)
    * VDD Voltage: 1.8 V
    * Power Consumption: 15 W at 1.8 V
    * Transistor Count: 10.5 Million
    * Die Area: 240 mm�
    * Chip Packaging: 540 Contact PBGA
    * Floating Point: 6.2 Billion Single Precision (32 Bit) Floating Point Operations a Second
    * Perspective Transformation: 66 Million Polygons a Second
    * With Lighting and Fog: 36 Million Polygons a Second
    * Bezier Surface Patches: 16 Million Polygons a Second
    * Image Decompression: 150 Million Pixels a Second

GPU: RSX "Reality Synthesizer" @ 550MHz

    * 550 MHz G70 based GPU on 90 nm process
    * 300+ million transistors (600 million with Cell CPU)
    * Multi-way programmable parallel floating-point shader pipelines
      > Independent pixel/vertex shader architecture
      > 24 parallel pixel pipelines, aligned in 6-way MIMD array
         > 5 ALU operations per pipeline, per cycle (2 vector4 or 2 scalar/dual/co-issue and fog ALU)
         > 27 FLOPS per pipeline, per cycle
         > 8 parallel vertex pipelines, aligned in 8-way MIMD array
            > 2 ALU operations per pipeline, per cycle (1 vector4 and 1 scalar, dual issue)
            > 10 FLOPS per pipeline, per cycle
         > Maximum vertex count:a lot probably over 1.2 billion vertices per second
            > Minimum (worst case) polygon count: 400 million polygons per second (1.2 billion vertices per second / 3 vertices per triangle)
            > Maximum (optimistic case) 750 million and more depending on how many triangle strips are used in the game
         > Maximum shader operations:100 billion shader operations per second ( 136 shader operations per clock cycle ).
         > Announced: 1.8 TFLOPS (trillion floating point operations per second) (2 TFLOPS overall performance)
    * 24 texture filtering units (TF) and 8 vertex texture addressing units (TA)
       > 24 filtered samples per clock
          > Maximum texel fillrate: 13.2 GigaTexels per second (24 textures * 550 MHz)
       > 32 unfiltered texture samples per clock, ( 8 TA x 4 texture samples )
    * 8 Render Output units
       > Maximum pixel fillrate: 4.4 GigaPixel per second (8 ROPs * 550 MHz)
       > Maximum Z sample rate: 8.8 GigaSamples per second (2 Z-samples * 8 ROPs * 550 MHz)
       > Maximum anti-aliasing sample rate: 8.8 GigaSamples per second (2 subsamples * 8 ROPs * 550 MHz)
    * Maximum Dot product operations: 51 billion per second
    * 128-bit pixel precision offers rendering of scenes with high dynamic range rendering (HDR)
    * 256 MiB GDDR3 RAM at 700 MHz
       > 128-bit memory bus width
       > 22.4 GiB/s read and write bandwidth
    * Cell FlexIO bus interface
       > 20 GiB/s read to the Cell and XDR memory
       > 15 GiB/s write to the Cell and XDR memory
    * Support for OpenGL ES 2.0
    * Support for S3TC texture compression


GPU: GS "Graphic Synthesizer" (20 & 60GiB USA/JAP/60GB PAL Models)

    * Clocked at 147 MHz
    * Pixel pipelines: 16
    * Video output resolution: variable from 256x224 to 1280x1024 pixels
    * 4 MB (MiB) Embedded DRAM video memory bandwidth at 48 GigaBytes per second (main system 32 MB can be dedicated into vram)
     > Texture buffer bandwidth: 9.6 GBytes/s
     > Frame buffer bandwidth: 38.4 GBytes/s
    * DRAM Bus width: 2560-bit (composed of three independent buses: 1024-bit write, 1024-bit read, 512-bit read/write)
    * Pixel Configuration: RGB: Alpha:Z Buffer (24:8, 15:1 for RGB, 16, 24, or 32-bit Z buffer)
    * Dedicated connection to: Main CPU and VU1
    * Overall Pixel fillrate: 16x147 = 2.352Gpixel/sec(rounded to 2.4Gpixel/sec)
    * Pixel fillrate: with no texture, flat shaded 2.4(75,000,000 32pixel real-world triangles)
    * Pixel fillrate: with 1 full texture(Defuse Map), Gouraud shaded 1.2 (37,750,000 32-bit pixel real-world triangles)
    * Pixel fillrate: with 2 full textures(Defuse map + specular or alpha or other), Gouraud shaded 0.6 (18,750,000 32-bit pixel real-world triangles)
    * Multi-pass rendering ability
       > Four passes = 300M pixels/second (300M pixel/sec divided by 32pixel = 9,375,000 triangle/sec lossed every four passes)

   
Sound:

    * Dolby 5.1ch, DTS, LPCM, etc. (Cell-based processing)


System Memory (Non Unified):

    * 256MB XDR Main RAM @3.2GHz
    * 256MB GDDR3 VRAM @700MHz


System Bandwidth:

    * Main RAM -- 25.6GB/s
    * VRAM -- 22.4GB/s
    * RSX -- 20GB/s (write) + 15GB/s (read)
    * SB -- 2.5GB/s (write) + 2.5GB/s (read)


System Floating Point Performance:

    * 2 TFLOPS


Storage:

    * Blu-Ray optical Drive
       > 2X Read (72Mbps)
    * Detachable 2.5" SATA-1HDD slot x 1
      > 20GB
      > 60GB
      > 80GB
      > 40GB
      > Expandable
         > Notebook SATA-1 5200 RPM Drive to 750GiB (750 highest known used)
    * Memory Card Reader (Model Specific)

I/O

    * SATA-1 HDD Controller
      > 750Mhz
    * USB Front x 4, Rear x 2 (USB2.0) (20, 60 & 80 GiB Models)
      > 2 Front (40Gb Model)
    * Memory Card Reader (60 & 80 GiB Model)
      > Memory Stick standard/Duo, PRO x 1
      > SD standard/mini x 1
      > CompactFlash (Type I, II) x 1


Communication:

    * Ethernet (10BASE-T, 100BASE-TX, 1000BASE-T)
    * Wi-Fi IEEE 802.11 b/g
    * Bluetooth 2.0 (+EDR)
      > 2402 - 2480 Ghz
      > 3.3vDC

US: FCC Regulations prohibit the simultaneous transceiving of Blue-Tooth and WLAN from a single unit.  Both transceiver arrays are multiplexed on and off to transceive opposite each other by turning each array on and off many times a second. 


Controller:

    * Bluetooth (up to 7)
    * USB 2.0 (wired)
    * Wi-Fi (PSP)
    * Network (over IP)


AV Output

    * Screen size: 480i, 480p, 720p, 1080i, 1080p
    * HDMI v1.3a out
    * Analog: AV MULTI OUT x 1
       > Composite
       > Component
       > SCART (PAL)
       > S-Video
       > VGA
    * Digital audio: DIGITAL OUT (OPTICAL) x 1
    * RCA Audio Out


Disc Media:

    *  CD PlayStation CD-ROM, PlayStation 2 CD-ROM, CD-DA, CD-DA (ROM), CD-R, CD-RW, SACD,
        SACD Hybrid (CD layer), SACD HD, DualDisc, DualDisc (audio side), DualDisc (DVD side)
        > No SACD 40GiB Model
    *  DVD: PlayStation 2 DVD-ROM, PlayStation 3 DVD-ROM, DVD-Video, DVD-ROM, DVD-R,
        DVD-RW, DVD+R, DVD+RW
    *  Blu-ray Disc: PlayStation 3 BD-ROM, BD-Video, BD-ROM, BD-R, BD-RE
        > Blu-Ray Java


Backward Compatibility Models PS1/PS2

    * 60Gb Model - Hardware (USA/JAP Only)
    * 20GB Model - Hardware (USA/JAP Only)
    * 80GB Model - Software (All Regions) Prior to September 2008
    * 40GB Model - Software PS1 Only

File System

    * Proprietary Fat32 Derived File System (HDD)
       > Encrypted Format
          > Formatted HDD Only works in console formatted on
       > Physical 4GB file (Fat32) size limit restriction does not apply
    * Memory cards for reader - Fat32
    * Linux (Other O/S)
       > Ubuntu
       > Fedora
       > Gentoo
       > Debian
       > Yellow Dog


File Extensions
   
    * .BLD = BootLoader - For Installing Other O/S
    * .PUP = File or patch used to update the PlayStation 3 (PS3) system software.
    * .PKG = Package - Downloaded Demos/Content In Compressed Format
    * .SELF = Recognized By GameO/S For Foreign BootLoaders
       > No longer required with V1.60 and up; use .BLD
    * .PSV = Native Game Save File Format
       > Digitally Signed

MISC
    * DivX / XviD Support With v2.10 firmware
    * DivX / XviD > 2GB File Support with v2.15 firmware

Max Drive 160 HDD (USB)

The PS3 is more than just a games console. It's a multimedia marvel which you can use to watch videos, listen to your MP3s and view your digital pictures such as holiday snaps, all from the comfort of; wherever you choose to put your PlayStation 3. But having access to all these digital delights present a problem of their own. Where do you put it all? Your PlayStation 3's hard drive may seem huge at first, but if you use it to store digital media such as photos, music and video, it soon fills up. Never fear - MAX Drive 160 for PS3 is here…

With MAX Drive 160 for PS3, you can expand your storage space by an incredible 160GB. Just plug it into your PS3, and you're ready to go. It's also the ideal file transfer solution too. Plug it into your PC, and you can drag and drop your movies, music and pictures onto your MAX Drive. You can then take it to your console and plug it in once more, and you have easy access to everything you copied. You don't even need a network!

But it's not just for media. With MAX Drive, you can store gamesaves and matierial downloaded from the PlayStation store, freeing up room on your PS3's hard drive, and moving it back when needed. With MAX Drive 160 is the ultimate multimedia companion for the PS3. Buy one, and you'll wonder how you ever did without it.
Free MAX Media Manager Pro!

MAX Drive 160 now comes with a FREE copy of MAX Media Manager Pro, the perfect PlayStation 3 media management solution which sells separately for £14.99. You can transfer MP3s to your supplied memory card, and even rip CDs. Video footage can be converted and condensed, and you can subscribe to Podcasts, manage your picture collection and even swap game saves with people from all over the world!

Features

    * Store your photos, movies and music.
    * External 160GB HDD.
    * Plug and play convenience.
    * Includes FREE copy of MAX Media Manager Pro for PS3.

PS3 HARD DRIVE MAPPING

Below is a file list from the hard disk.  Some directories are still inaccessible, but there is a small list none the less.  This is from a development (debug) kit.

The BCUS98107 entry is that of Resistance: Fall of Man.  You will see its files are cache files, copied to the HDD.
---------------------------------------------------------------------------------------

./dev_hdd0:
.
..
data
drm
dump.txt
game
home
mms
vsh
widget

./data:
.
..
bootflag.dat

./drm:
.
..

./game:
.
..
ABCD67890
BCUS98107
BLUS30014
NPSX00002
SXXX00001

./game/ABCD67890:
.
..
PARAM.SFO
USRDIR

./game/ABCD67890/USRDIR:
.
..
ENTRY-DATA

./game/BCUS98107:
.
..
ICON0_00.PNG
ICON0_09.PNG
ICON0.PNG
PARAM.SFO
PIC1.PNG
USRDIR

./game/BCUS98107/USRDIR:
.
..
cache
data
quick.sav

./game/BCUS98107/USRDIR/cache:
.
..
credits_0.bnk
credits_0.bnk.done
credits_0.bnkh
credits_0.bnkh.done
credits.d.pkg
credits.d.pkg.done
credits.e.pkg
credits.e.pkg.done
credits.f.pkg
credits.f.pkg.done
credits.g.pkg
credits.g.pkg.done
credits.ig
credits.ig.done
credits.i.pkg
credits.i.pkg.done
credits.j.pkg
credits.j.pkg.done
credits.k.pkg
credits.k.pkg.done
credits.p.pkg
credits.p.pkg.done
credits.s.pkg
credits.s.pkg.done
credits.u.pkg
credits.u.pkg.done
global_config.dat
global_config.dat.done
global_config.d.dat
global_config.d.dat.done
global_config.e.dat
global_config.e.dat.done
global_config.f.dat
global_config.f.dat.done
global_config.g.dat
global_config.g.dat.done
global_config.i.dat
global_config.i.dat.done
global_config.j.dat
global_config.j.dat.done
global_config.k.dat
global_config.k.dat.done
global_config.p.dat
global_config.p.dat.done
global_config.s.dat
global_config.s.dat.done
global_config.u.dat
global_config.u.dat.done
global_core_text.d.dat
global_core_text.d.dat.done
global_core_text.e.dat
global_core_text.e.dat.done
global_core_text.f.dat
global_core_text.f.dat.done
global_core_text.g.dat
global_core_text.g.dat.done
global_core_text.i.dat
global_core_text.i.dat.done
global_core_text.j.dat
global_core_text.j.dat.done
global_core_text.k.dat
global_core_text.k.dat.done
global_core_text.p.dat
global_core_text.p.dat.done
global_core_text.s.dat
global_core_text.s.dat.done
global_core_text.u.dat
global_core_text.u.dat.done
global_font_data.dat
global_font_data.dat.done
global_font_data.k.dat
global_font_data.k.dat.done
global_font_data.lobby.dat
global_font_data.lobby.dat.done
global_font_texture.k.tp
global_font_texture.k.tp.done
global_font_texture.k.tph
global_font_texture.k.tph.done
global_font_texture.lobby.tp
global_font_texture.lobby.tp.done
global_font_texture.lobby.tph
global_font_texture.lobby.tph.done
global_font_texture.tp
global_font_texture.tp.done
global_font_texture.tph
global_font_texture.tph.done
global_fx_texture.tp
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pause_83.bnkh
pause_83.bnkh.done
pause_84.bnk
pause_84.bnk.done
pause_84.bnkh
pause_84.bnkh.done
pause_85.bnk
pause_85.bnk.done
pause_85.bnkh
pause_85.bnkh.done
pause_8.bnk
pause_8.bnk.done
pause_8.bnkh
pause_8.bnkh.done
pause_9.bnk
pause_9.bnk.done
pause_9.bnkh
pause_9.bnkh.done
pause.d.pkg
pause.d.pkg.done
pause.e.pkg
pause.e.pkg.done
pause.f.pkg
pause.f.pkg.done
pause_fxconduit.dat
pause_fxconduit.dat.done
pause.g.pkg
pause.g.pkg.done
pause.ig
pause.ig.done
pause.i.pkg
pause.i.pkg.done
pause.j.pkg
pause.j.pkg.done
pause.k.pkg
pause.k.pkg.done
pause.p.pkg
pause.p.pkg.done
pause_sound.dat
pause_sound.dat.done
pause.s.pkg
pause.s.pkg.done
pause.u.pkg
pause.u.pkg.done

./game/BCUS98107/USRDIR/data:
.
..

./game/BLUS30014:
.
..

./game/NPSX00002:
.
..
ICON0.PNG
PARAM.SFO
PS3LOGO.DAT
USRDIR

./game/NPSX00002/USRDIR:
.
..
EBOOT.BIN
sample.edat
sample.png

./game/SXXX00001:
.
..
ICON0.PNG
PARAM.SFO
PS3LOGO.DAT
USRDIR

./game/SXXX00001/USRDIR:
.
..
EBOOT.BIN

./home:
.
..

./mms:
.
..

./vsh:
.
..

./widget:
.
..

PS3 MAINBOARD HARDWARE - Originally by: 0m1kr0n - Updated by Powerslave

Updated 7/6/08

Items for the initial 20/60GB USA and JAP models are indicated as (USA/Jap Hardware Emu). Those parts are not in the EU/PAL versions, or the 80GB & 40GB models.  They are either removed, and/or replaced with another chip, and relocated.

Back of Mainboard:
- Samsung K9F1G08U0A is 1GB SLC NAND Flash
- NEC / TOKIN 0E128 is a Proadlizer - High Speed Decoupler

Top Side of Mainboard:
- Marvell 88E6108-LAR1 is an Ethernet Controller
- Silicon Image Sil9132CBU is HDMI Transmitter (output)
- Sony CXM4024R is only known as ASIC B outside Sony (USA/JAP Hardware Emu)

Sony Computer and Entertainment Inc., CXM4024R, © & (M), 2005SCEI, 628D30V

- Sony CXD9280GP - ?  Next to ASIC B Chip
- Marvell 88SA8040-TBC1 is a SATA controller
- Sony CXD2973GB (Above CELL) "0611HAL" Hardware Abstraction Layer (USA/JAP Hardware Emu)
- Sony CXD2979GB (Above CELL) "0629HAL" Hardware Abstraction Layer (Software Emu Boards)
- Sony CXD2973GB (Left of RSX) Microcontroller - Part of Southbridge  (Software Emu Boards)
- Sony CXD4302GB is I/O Bridge Controller
- Samsung K4Y50164UC-JCB3 is 256MB of XDRTM DRAM

Specs on ram say XDRTM DRAM 512Mbit XDR TM DRAM(C-die) - You need eight chips for 512MB total, and PS3 only has 512 total, 256/256 split.  The 256MB video ram is built into the RSX chip.

- Sony CXD2964GB Cell BBE/Core Processor.
- NEC/TOKIN 0E128 is a Proadlizer - High Speed Decoupler
- Sony CXD2971GB is the RSX GPU (w/256MB GDDR3 VRAM)
- Samsung K4J52324QC-SC14 256MB GDDR RAM (on GPU)

Specs on ram say 512Mbit GDDR VRAM, same notation as above with XDR Ram.  It is false, there is only 256MB for CPU and 256MB for GPU.

- Sony CXR713120 - PS1 Backward Compatibility Related (USA/JAP Hardware Emu) - known as ASIC A. Here's a quote from an Asian parts site:

Sony Computer and Entertainment Inc., CXR713120, © & (M) 2006SCEI,-201GB, 640A69W

- Sony CXD2953AGB is the Emotion Engine & Graphics Synthesizer Chip (USA/JAP Hardware Emu)
- Samsung K9F1G08U0A is 1GB SLC NAND Flash
- Toshiba (MFG Not printed on chip) CXD9208GP PS2 Legacy ASIC (NTSC/JAP Hardware Emu)
- ?MFG? 32 MB RDRAM "Rambus" (USA/JAP Hardware Emu)
- Genesys Logic GL852 - USB2.0 HUB CONTROLLER w/8BIT RISC Processor

Blu-Ray Board:
- Sony CXD5064R is an audio Decoder
- Spansion S99-50111-001 is 16MB Flash memory
- Sony CXA2720R is a Blu-Ray interface controller
- Sony CXD5063GG-1 ASIC / CPU - Video Decryption Chip
- Samsung K4S641632K-UC75 64MB SDRAM
- S!PWM is a timer chip - Pulse Width Modulator (controls laser and spindle) Has EEPROM and RAM

Wifi Board
- SCEI&SCR "D3261GG" (Bluetooth transceiver?)
- Spansion S99AL008D002 NOR FLASH 8MB 3.3V
- Marvell 88W8010-NNB1 Optimized RF-baseband transceiver, integrates at near 20 dBm
- ISSI IS42S32400B 128MB SRAM
- Marvell 88W8580-BAN1 802.11g 56Mbps WLAN

Controller Board Front
- SCEI&SCR "D3261GG" (Bluetooth transceiver?)
- 325A (?)

Controller Board Back
- Toshiba T6UM2EFG-0103 (Gyroscope/Motion Sensor? Centered)

UNUSED PS3 MOTHERBOARD CHIPSET PORTS:
3x TSIF Digital Video In
Analog Video In
Analog Audio In
3x Video Out (HDMI,D4,A-DAC)
IEEE1394 Firewire
1x PATA (IDE)

KEY TO TERMS:
HAL = Hardware Abstraction Layer: Binary code that allows a portion of the operating system that lets programs deal with hardware directly. This allows programs needing more speed from the computer to bypass the standard OS calls to hardware.  The PS3 Hypervisor prevents this access needed for unlocking the full potential under Linux or with hacking the PS3.

ASIC = Application-Specific Integrated Circuit: An IC that is customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run on the PS3 is an ASIC.  In the case of the PS3, they are for the hardware PS2/1 emulation on the USA/JAP models with the EE+GS.

PROADLIZER = This device easily resolves two opposing needs: higher speeds and performance, and weight reduction and miniaturization.  This device replaces numerous capacitors used for decoupling circuits such as high-frequency resonant ceramic capacitors, large-capacity ceramic capacitors, and alminum (not aluminum) electrolytic capacitors. It was developed for CPU decoupling circuits, for PCs and servers, which have serious decoupling circuit problems.

NOR FLASH = http://en.wikipedia.org/wiki/Flash_memory#NOR_flash

NAND FLASH = http://en.wikipedia.org/wiki/Flash_memory#NAND_flash

SLC (FLASH) = Single-Level Cell: SLC NAND Flash’s control logic does a better job conserving energy than MLC (Multi-Layer Cell). This is primarily because the device only needs to manage the electrical charge for two states and one bit of stored data. As a result, SLC architectures offer a significantly greater cycle endurance as compared to MLC.